This invention relates generally to methods of interconnecting processor circuits, and more particularly to methods of interconnecting large numbers of signal processors to a general-purpose computer bus using serial interfaces.
Since the development of the earliest computers, there has been a trend toward increasing the size and complexity of bus architectures in general-purpose computers. Increases in bus width have allowed for performance improvements, because a wider bus can carry more information at a given speed. Increases in complexity have added a range of functions, such as bus mastering, bus segmentation, automatic configuration, and high-speed burst transfer capabilities to older, simpler microprocessor interfaces, which typically only included data lines, address lines, and a few control lines.
Although the newer architectures are more complicated, some of them, such as the so-called Peripheral Component Interconnect (PCI) bus, have received widespread industry acceptance. The resulting economies of scale have lead to reductions in the cost of compatible peripherals that more than outweigh the higher complexities of the bus standard, and integrated circuit manufacturers have responded to this trend by developing bridge circuits to capitalize on the benefits of these newer bus structures. These typically include circuitry that interfaces with the more complex general-purpose bus architectures connected to circuitry that interfaces with the simpler bus control interfaces of one or more peripheral integrated circuits.
In one general aspect, the invention features a signal processing system that includes a control processor that has a bi-directional port, signal processors that each have a serial port, a bridge that has serial ports each operatively connected to a serial port of one of the signal processors, and a bi-directional port operatively connected to the bi-directional port of the control processor.
The bridge can include bus mastering circuitry operatively connected to further bus mastering circuitry on a bus that operatively connects the control processor and the bridge. The bridge can include bus arbitration circuitry. The bridge can include buffer storage areas each responsive to one of the serial ports. The signal processors can each include local, parallel-word, random-access memory. The signal processors can each include a dedicated multi-bit shifter circuit, and a dedicated parallel-word multiplier circuit. The signal processors can each include digital signal processing code. The signal processors can each include media processing code. The signal processors form parts of different integrated circuits. The signal processors, the control processor, and the bridge can form parts of different integrated circuits. The signal processors, the control processor, and the bridge can be housed within a single computer system housing. The signal processors and the bridge can be located on a common circuit substrate. The serial ports of the bridge can be directly connected to the serial ports via a serial line that operates at least about 1 MHz. The serial ports of the bridge can be directly connected to the serial ports via a serial line that operates at least about 50 MHz. The bidirectional port can be a parallel port. The bridge can include bus mastering circuitry operatively connected to further bus mastering circuitry on a bus that operatively connects the control processor and the bridge. The bus can be a segmented bus with the control processor and bridge interconnected within a first segment that is operatively connected to other bus segments via further inter-segment bridges. The bus can be a segmented bus with the control processor and the bridge being interconnected by an inter-segment bridge. The serial ports of the bridge can each include a data ready input, a clock output, and clock stalling circuitry responsive to the data ready input and operatively connected to the clock output. The bridge can include bus arbitration circuitry with the bus arbitration circuitry being operatively connected to the clock stalling circuitry.
In another general aspect, the invention features a signal processing system that includes processor means having a bidirectional port, a plurality of signal processing means each having a serial port, and means for transferring data between the bidirectional port and the serial ports.
The means for transferring data can include means for requesting mastery of an interconnection path between the means for transferring and the processor means. The signal processing means can include media signal processing means. The signal processing means can each include means for locally storing and retrieving data. The bidirectional port can be a parallel port. The means for transferring data can include means for stalling a clock associated with one of the signal processors in response to a request from one of the signal processing means.
In a further general aspect, the invention features a signal processing method that includes computing with a first processor, computing with a second processor, shifting a first data word between the first processor and a bridge, shifting a second data word between the second processor and a bridge, parallel transferring the first data word between a third processor and the bridge, and parallel transferring the second data word between the third processor and the bridge.
The first and second steps of shifting can respectively shift the first and second data words from the first and second processors to the bridge, with the steps of parallel transferring transferring the first and second data words from the bridge to the third processor after the steps of shifting, and further including the step of storing the first data word in the bridge after the step of shifting the first data word and before the step of parallel transferring the first data word, and the step of storing the second data word in the bridge after the step of shifting the second data word and before the step of parallel transferring the second data word. The method can include issuing and granting a bus mastering request before at least one of the steps of parallel transferring to permit the at least one of the steps of parallel transferring. The step of computing the data word can include performing at least one media manipulation operation. The step of computing can include steps of storing and retrieving data in local processor memory.
In another general aspect, the invention features a bus bridge that includes serial ports, serial port interfaces operatively connected to the serial ports, a primary data port, and a primary data port interface operatively connected to the primary data port. The primary data port interface includes storage for burst transfers from the bus. The bridge further includes a data path between the serial port interfaces and the general-purpose bus interface and control circuitry operatively connected to the serial ports and to the general-purpose bus interface.
The control circuitry can include arbitration circuitry to arbitrate between requests from the serial ports to transfer data from the serial ports to the bus. The primary data port interface can include bus mastering logic to request master control of a general purpose bus in response to bus mastering requests from the serial ports. Each of the serial port interfaces can include a buffer storage area. The primary data port can include a connector adapted to interface with a segmented general-purpose bus with the primary data port interface enabling the bridge to communicate with processors through at least one inter-segment bridge separating segments of the general-purpose bus. The serial ports can include two data lines and two handshaking lines. The serial ports of the bus bridge can each include a data ready input, a clock output, with the serial port interfaces each including clock stalling circuitry responsive to the data ready input and operatively connected to the clock output. The bridge can further include bus arbitration to arbitrate between requests from the serial ports to transfer data from the serial ports to the bus, with the arbitration circuitry being operatively connected to the clock stalling circuitry.
In a further general aspect, the invention features a bus bridge that includes a plurality of means for communicating serial data signals, means for communicating parallel data signals, and means for transferring bursts of data signals between the plurality of means for communicating serial data signals and the means for communicating parallel data signals.
The bridge can include means for performing an arbitration to determine the relative priorities of data for the plurality of means of communicating serial data signals. The means for transferring can include means for causing the means for communicating parallel data signals to request bus master control in response to bus mastering requests from the means for communicating serial data signals. Each of the means for communicating serial data signals can include means for storing serial signals. The plurality of means for communicating serial data signals can each include means for stalling a clock in response to a transfer request signal.
In another general aspect, the invention features a signal interfacing method that includes selecting a first of a plurality of serial data ports in a bus bridge, communicating bursts of serial data signals between the first of the plurality of serial data ports and a primary data port, wherein the step of communicating bursts of serial data signals includes communicating an address word and a plurality of data words, selecting a second of the plurality of serial data ports in a bus bridge, and communicating bursts of further serial data signals between the first of the plurality of serial data ports and the primary data port, wherein the step of communicating bursts of further serial data signals includes communicating an address word followed by a plurality of data words. The method can further include the steps of requesting mastership of a communication medium and receiving mastership of the medium before the steps of communicating serial data signals with the steps of communicating taking place over the communication medium.
In a further general aspect, the invention features a bus bridge that includes a plurality of serial ports, a plurality of serial port interfaces operatively connected to the serial ports, a primary data port, and a primary data port interface operatively connected to the primary data port, with the primary data port interface including bus mastering capabilities. The bridge also includes a data path between the serial port interfaces and the general-purpose bus interface and control circuitry operatively connected to the serial ports and to the general-purpose bus interface.
The control circuitry can include arbitration circuitry to arbitrate between requests from the serial ports to transfer data from the serial ports to the bus. The primary data port interface can include bus mastering logic to request master control of a general purpose bus in response to bus mastering requests from the serial ports. Each of the serial port interfaces can include a buffer storage area. The primary data port can include a connector adapted to interface with a segmented general-purpose bus and the primary data port interface can enable the bridge to communicate with processors through at least one inter-segment bridge separating segments of the general-purpose bus. Each of the serial ports can include two data lines and two handshaking lines. The serial polls of the bus bridge can each include a data ready input, a clock output, with the serial port interfaces each including clock stalling circuitry responsive to the data ready input and operatively connected to the clock output. The bridge can further include bus arbitration circuitry to arbitrate between requests from the serial ports to transfer data from the serial ports to the bus, with the arbitration circuitry being is operatively connected to the clock stalling circuitry.
In another general aspect, the invention features a bus bridge that includes a plurality of means for communicating serial data signals, means for communicating parallel data signals, and means for transferring data signals between the plurality of means for communicating serial data signals and the means for communicating parallel data signals, wherein the means for transferring includes bus mastering means.
The bridge can include means for performing an arbitration to determine the relative priorities of data for the plurality of means of communicating serial data signals. The means for transferring can include means for causing the means for communicating parallel data signals to request bus master control in response to bus mastering requests from the means for communicating serial data signals. Each of the means for communicating serial data signals can include means for storing serial signals. The plurality of means for communicating serial data signals can each include means for stalling a clock in response to a transfer request signal.
In a further general aspect, the invention features a signal interfacing method that includes selecting serial data ports in a bus bridge, communicating serial data signals between the serial data ports and a primary data port, selecting a second of the plurality of serial data ports in a bus bridge, and communicating further serial data signals between the first of the plurality of serial data ports and the primary data port.
Systems according to the invention may be advantageous in that they permit the manufacture of low-cost, high efficiency, multi-processor circuits, such as media signal processing peripherals for general-purpose computers. Because such systems employ serial interfaces that require fewer interconnections, they can be smaller, less expensive, or both. The serial interfaces may also include fewer high-power interface driver circuits than do full-width parallel bus interfaces, so that power consumption of the peripheral can be reduced. In addition, although each serial interface may have a lower bandwidth than a high-speed burst-based bus with which it exchanges data, the overall throughput between the signal processors and the bus can approach that of the bus itself. And by interweaving this serial topology with a scalable segmented bus architecture, an interdependent clustered structure that compounds the above advantages can be achieved.